Energy Efficiency

(Thrust leader: Ali Niknejad, UC Berkeley)

TxACE is committed to alleviate the global energy problem by improving the energy efficiency of electronic systems as well as by developing analog technologies that can make energy generation, distribution and utilization more efficient. The Center is also working to energize and power long-lasting in-situ microscale devices such as wireless microsensors, biomedical implants, and portable microelectronics. The research in this thrust includes power converters, co-optimization of converters and regulators with systems powered by them, I/O with power consumption that scales with the data rate, optimization of TSV placement for thermal management, efficient drivers for a power stage with reduced EMI, ultra low-power analog to digital converters, ultra-capacitors formed using carbon nano-tubes, a fast start-up crystal oscillator with reduced power consumption, built-in self-test for power management IC’s, System-In-Package energy harvester and others.

Figure 4. (Left) Baud rate receiver for energy efficient I/O (P. Hanumolu, UIUC), (Top center) System-in-package energy harvester (S. Mukhopadhyay, Georgia Tech.), (Bottom center) Simulated cross-sectional temperature distribution with TSV’s (J. Lee, N. Bagherzadeh, UC-Irvine), (Right) The first interleaved noise-shaping SAR ADC. It also uses for the first time a four-stage ring amplifier (M. Flynn, U. of Michigan).

Energy Efficiency Thrust



Category Accomplishment
Energy Efficiency (Circuits) State-of-the-art low-power ADCs are difficult to drive as they require a filter and an input buffer, and are limited in either resolution or power consumption. To overcome these limitations, the first interleaved noise-shaping SAR ADC that uses the first four-stage ring amplifier is demonstrated. The ADC achieves a measured resolution of 15b. This new class of converters will facilitate and improve sensing and IoT applications. (2712.007, M. Flynn, U. Michigan)
Energy Efficiency (Systems) The gate driving strength should be low before the starting point of Miller Plateau to reduce di/dt for lower EMI noise. Subsequent to this point, the drive strength should be increased rapidly to achieve a high dv/dt for low power loss. This observation has been utilized to realize a GaN DC-DC Buck converter with an adjustable gate driver stage in a custom 0.18-µm HV CMOS process to achieve 119% higher peak-EMI attenuation, and 3 times higher VO-jittering suppression than the state of art. (2810.006, B. Ma, UT Dallas)
Energy Efficiency (Circuits) Integrated voltage regulation of fine-grained voltage domains is accomplished through use of a resonant-clocked SIMO buck converter and addressing the accompanying challenges of severely degraded load regulation through a novel unified clock-regulator architecture. The first computationally controlled LDO for rapidly settling VDD, and auto-tuning of loop-gain is demonstrated in 65-nm CMOS. (2712.006, V. Sathe, U. Washington)
Energy Efficiency (Circuits) The goal of this project is to realize a mostly digital, high-order VCO based Delta-Sigma ADC. A prototype of VCO-based CT ADC has a record low measured Walden FoM of 8.6fJ/step with a 100-µW power consumption. (2712.020, A. Sanyal, U. Buffalo)