Energy Efficiency

(Thrust leader: Ali Niknejad, UC Berkeley)

TxACE is committed to alleviate the global energy problem by improving the energy efficiency of electronic systems as well as by developing analog technologies that can make energy generation and distribution more efficient. The Center is also working to energize and power long-lasting in-situ microscale devices such as wireless microsensors, biomedical implants, and portable microelectronics.

Figure 4. (Top left) Resonant converter for isolated power transfer (B. Ma, UT-Dallas), (Top right) Dynamic BIST for LDO’s (S. Ozev, Arizona State U.), (Bottom left) BER versus SNR for PLC/Wireless receiver combining techniques based on maximal-ratio-combining that take into account the impulsive nature of noise on the two links (N. Al-Dhahir, UT-Dallas, B. Evans, UT-Austin), (Bottom center) Micro-power three step incremental ADC (G. Temes, Oregon State U.), (Bottom right) Simulated cross-sectional temperature distribution in a 8-row TSV arrangement (J. Lee, N. Bagherzadeh, UC-Irvine).

Energy Efficiency Thrust



Category Accomplishment
Energy Efficiency (Circuits) A novel gate-leakage-based frequency locking timer has been proposed that achieves 260ppm/oC from -5oC to 95oC while only consuming 224 pW at 90-Hz output frequency and less than 1%/V supply dependence over a wide range of 1.1V-3.3V. The circuit uses 1st and 2nd order cancellation over temperature to realize the performance. (2810.009, D. Sylvester, U. Michigan)
Energy Efficiency (Systems) IoT devices and sensor nodes must be able to wake up quickly and transmit and receive data in order to maximize energy efficiency. Crystal wakeup time is often the dominant limit due to the high Q of resonator. A technique that reduces the startup time by more than 15X over an extended temperature range is demonstrated. Techniques are being developed to relax the precision requirements of the injection oscillator. (2810.008, S. Pamarti, UCLA)
Energy Efficiency (Circuits) Energy proportional links have the potential to greatly lower power consumption of practical systems where high power in the high speed links implies high efficiency only during high speed communication. A sub-baud rate clock and data recovery technique is being developed to further lower power consumption. To date a 15 Gb/s 1.9 pJ/b link has been demonstrated with a 15-MHz JTOL bandwidth. (2712.009, P. Hanumolu, UIUC)
Energy Efficiency (Circuits) Efficient multi-voltage domain digital SoC power management is accomplished through integrated voltage regulation of fine-grained voltage domains using a resonant-clocked SIMO buck converter. Load regulation is solved by an accompanying unified clock-regulator architecture. A prototype in 65-nm CMOS utilizes a 64-bank 2:1 SC with continuous supply scalability. Droop margins and PVT variations on a Cortex M0 + FFT co-processor have been characterized with 94% average recovery of supply margins. A second test-chip demonstrates an all-digital single phase buck architecture with 82% recovery of voltage margins. (2712.006, V. Sathe, U. of Washington)