Fundamental Analog Circuits Research

(Thrust leader: Pavan Hanumolu, U. of Illinois Urbana-Champaign)


Research in this thrust focuses on cross-cutting areas in analog and mixed signal circuits which impact all of the TxACE application areas (Energy Efficiency, Public Safety and Security, Health Care). The list of research includes design of a wide variety of analog-to-digital converters, communication links, temperature sensors, I/O circuits, noise reduction techniques, new amplifier topologies suitable for use in nano-scale CMOS, development of CAD tools and testing of integrated circuits.

Figure 5. (Top left) Hierarchical analog and mixed-signal verification using hybrid formal and machine learning techniques (P. Li, UC Santa Barbara), (Top center) Performance of new clock multiplier architecture that is immune to frequency drift (A. Niknejad, UC Berkeley), (Bottom left) Ring amplifier based LDO (U. Moon, Oregon State U.), (Bottom center) Simulation of fields inside transitions and a dielectric waveguide (R. Henderson, UT Dallas), (Right) 3rd order continuous-time delta-sigma modulator with excess loop delay compensation using digital information stored on the input parasitic capacitance of a comparator (Nima Maghari, U. of Florida).

Fundamental Analog Thrust

 

 

Category Accomplishment
Fundamental Analog (Circuits) A 3-GHz 8X clock multiplier with a jitter performance that is insensitive to frequency drift without using a continuous frequency tracking loop (FTL) is demonstrated. Using digital calibration techniques, the spurs are effectively suppressed down to -50.9 dBc. Fabricated in 28-nm CMOS technology, this prototype achieves an integrated jitter of 138 fs,rms while consuming 6.5 mW from a 1-V/0.8-V supplies and achieves -249-dB FoM. (2810.007, PI: Ali Niknejad)
Fundamental Analog (Circuits) Excess loop delay (ELD) compensation using digital information stored on the input parasitic capacitance of a comparator is proposed to obviate the need for a dedicated ELD compensation circuit. The non-linear parasitic capacitance is linearized by maintaining the input transistor pair always in one region of operation. A 3rd order continuous-time delta-sigma modulator fabricated in a 0.13-μm CMOS process is used to validate the concept. The prototype ADC operates at 500 MHz sampling frequency, and achieves a peak SNDR of 74.4 dB and a peak SNR of 76.2 dB over a 15-MHz bandwidth while consuming 10.1 mW from a 1.2-V supply. (2712.014, PI: Nima Maghari)
Fundamental Analog (Circuits) High data rate 180-GHz MSK modulated signals for dielectric waveguide communication with an output power of -3.5 dBm are demonstrated using a signal generator fabricated in 65-nm CMOS. Limited by the instrumentation for MSK signal analyses, the eyes of transmitted MSK signals have been verified for a data rate up to 10 Gbps. The spectra of transmitted signals for data rate up to 15 Gbps are also demonstrated. The MSK signal generator provides 5X higher data rate among all the previously reported MSK transmitters at 3X higher carrier frequency. (2810.015, PI: Ken O)