Fundamental Analog Circuits Research

(Thrust leader: Pavan Hanumolu, U. of Illinois Urbana-Champaign)


Research in this thrust focuses on cross-cutting areas in Analog Circuits which impact all of the TxACE application areas (Energy Efficiency, Public Safety and Security, Health Care). The list of research includes design of a wide variety of analog-to-digital converters, communication links, temperature sensors and I/O circuits, development of CAD tools, and testing of integrated circuits.

Figure 5. (Left) Configurable frequency-domain ADC-based receiver (S. Palermo, Texas A&M), (Top center and Bottom right), 30-Gbps data from a 300-GHz QPSK transmitter (K. O, UT Dallas), (Top right) Precision Voltage Reference using Bandgap Separator and thermal Function Generator (R. Geiger, Iowa State U.).

Fundamental Analog Thrust

 

 

Category Accomplishment
Fundamental Analog (Circuits) A mixed-signal PAM4 quarter-rate receiver employs a single-stage CTLE and a DFE with 1 FIR and 1 IIR-tap to efficiently compensate for more than 20dB channel loss. An edge-based sampler is used to perform both PLL-based CDR phase detection and adaptation of the DFE tap coefficients in background. Fabricated in GP 65-nm CMOS, the 56Gb/s receiver achieves 4.63mW/Gb/sec when operated with a 2-tap FFE transmitter. (1836.143, PI: Sam Palermo, Texas A&M)
Fundamental Analog (Circuits) Techniques for spur and phase noise cancellation are developed. A delay-and-interpolate method introduces notches to suppress spurs. A delay-line discriminator extracts phase noise and a feed-forward loop cancels out input phase noise. Fabricated in a 65-nm CMOS process, the spurs are suppressed by more than 15dB and the phase noise at offset frequencies in the range of 4MHz-200MHz from a 1.4-GHz carrier is improved by a maximum of 25dB. (2810.007, PI: Ali Niknejad, UC Berkeley)
Fundamental Analog (Circuits) A 300-GHz 30-Gbps QPSK transmitter consists of an on-chip multi-mode modulator, an injection locked quadrature oscillator, a 40-GHz bandwidth power amplifier with constant gain and group delay, a 4X frequency multiplier chain to generate a 165-GHz LO signal for a double balanced up-conversion mixer that generates the output at 300 GHz. The transmitter without equalization consumes 180mW with an energy efficiency of 6 pJ/bit. (1836.152, PI: Ken O, UT Dallas)