Fundamental Analog Circuits Research

Research in this thrust focuses on cross-cutting areas in Analog Circuits which impact all of the TxACE application areas (Energy Efficiency, Public Safety and Security, Health Care). The list of research includes design of a wide variety of analog-to-digital converters, communication links, temperature sensors and I/O circuits, development of CAD tools, and testing of integrated circuits.

Figure 1. (Left) Low cost ultra-pure sine wave generation with self-calibration. (D. Chen, R. Geiger, Iowa State), (Top right), 12-b 330MS/s single-channel pipelined-SAR ADC (Y. Chiu, UT Dallas), (Bottom center) 2-2.8GHz 65-nm CMOS ring oscillator PLL (P. Kinget, Columbia), (Bottom right) DLL-based clock generation, with phase picking controlled by tunable replica circuits (B. Nikolic).

Fundamental Analog Thrust



Category Accomplishment
Fundamental Analog (Circuits) A RISC-V system-on-chip with integrated voltage regulation and power management is implemented in 28-nm FD-SOI. A fully integrated switched-capacitor DC-DC converter, coupled with an adaptive clocking system, achieves 82-89% system conversion efficiency across a wide operating range, yielding a total system efficiency of 41.8 double-precision GFLOPS/W. (1836.136, PI: B. Nikolic, UC-Berkeley)
Fundamental Analog (Circuits) A 12-b 330MS/s single-channel pipelined-SAR ADC employs a PVT-stabilized dynamic amplifier as the residue amplifier instead of opamp-based residue amplifiers that consume significant amounts of power due to stringent settling speed and accuracy requirements. The ADC fabricated in 65-nm CMOS with a core area of 0.08mm2 achieves an FoM of 9.5fJ per conversion. The measured DNL and INL are +0.67/-0.56LSB and +0.7/-0.8LSB, respectively. The measured SNDR remains above 60dB even with a 500MHz input. (1836.157, PI: Y. Chiu, UT-Dallas)
Fundamental Analog (Circuits) A 2-2.8GHz 65-nm CMOS ring oscillator PLL occupies an active area of 0.022 mm2, consumes 5.86mW, and achieves a 633fs RMS jitter at 2.36 GHz and an FOMjitter of -236 dB. It implements a low-overhead feed-forward phase and supply-noise cancellation scheme by leveraging the noise extraction inherently done by the sub-sampling phase detector. Cancellation reduces the jitter by 1.4X, the phase noise by 10.2dB to -123.5dBc/Hz at a 300KHz offset, and the ring oscillator supply sensitivity by 19.5dB for a 1-mVp-p 100KHz supply noise tone. (1836.134, PI: P. Kinget, Columbia University)